AMD announces Versal Premium Series Gen 2 enabling new levels of system acceleration to meet the demands of data-intensive workloads
AMD announced the AMD Versal Premium Series Gen 2, an adaptive SoC platform designed to deliver the highest levels of system acceleration for a wide range of workloads. Versal Premium Series Gen 2 will be the FPGA industry’s first devices featuring Compute Express Link (CXL) 3.1 and PCIe Gen6 as well as LPDDR5X memory support in hard IP.
These next-generation interface and memory technologies access and move data rapidly and efficiently between processors and accelerators. CXL 3.1 and LPDDR5X help unlock more memory resources faster to address the growing real-time processing and storage demands of data-intensive applications in data center, communications, test and measurement, and aerospace and defense markets.
“System architects are constantly looking to pack more data into smaller spaces and move data more efficiently between parts of the system,” said Salil Raje, senior vice president and general manager, Adaptive and Embedded Computing Group, AMD. “Our latest addition to the Versal Gen 2 portfolio helps customers improve overall system throughput and utilisation of memory resources to achieve the highest performance and unlock insights for their most demanding applications from the cloud to the edge.”
Accelerate Host Connectivity
AMD champions open innovation through its support of CXL, an open industry-standard interconnect between processors and devices such as FPGA-based accelerators. With support for CXL 3.1 and PCIe Gen6, the industry’s fastest host interfaces, Versal Premium Gen 2 devices enable industry-leading, high-bandwidth host CPU-to-accelerator connectivity. PCIe Gen6 offers a 2-4X faster line rate compared to competing FPGAs with PCIe Gen4 or Gen5 support,2 while CXL 3.1 running PCIe Gen6 provides double the bandwidth of competing devices with CXL 2.1 at similar latencies, as well as enhanced fabric and coherency capabilities.
Additionally, by pairing Versal Premium Series Gen 2 with an AMD EPYC™ CPUs, system architects can leverage the latest AMD FPGA-based device connected via CXL or PCIe to a high-performance CPU, to accelerate data-intensive applications and meet rapid data growth demands. CXL also brings an additional benefit of memory coherency to help enable true heterogeneous, accelerated computing.
Increasing Memory Bandwidth and Utilisation
AMD Versal Premium Series Gen 2 adaptive SoCs accelerate memory bandwidth for faster data transfers and real-time responsiveness with the fastest LPDDR5X memory connectivity available, at up to 8533 Mb/s. This ultra-fast, enhanced DDR memory enables up to 2.7X faster host connectivity over comparable competitive devices with LPDDR4/5 memory.
Connectivity to CXL memory expansion modules enable up to 2.7X more total bandwidth than LPDDR5X memory alone.5 As a result, the Versal Premium Series Gen 2 allows for scalable memory pooling and extension for multiple accelerators, optimising memory utilisation and increasing bandwidth and capacity.
By dynamically allocating a memory pool for multiple devices, Versal Premium Series Gen 2 adaptive SoCs are designed to improve memory utilisation in a Multi-Headed Single Logic Device (MH-SLD), allowing it to operate without a fabric or switch, while supporting up to two CXL hosts.
Strengthen Data Security
Enhanced security features help the Versal Premium Series Gen 2 transfer data quickly and securely, both in transit and at rest. It is the industry’s first FPGA device to feature support for integrated PCIe Integrity and Data Encryption (IDE) in hard IP.6 Inline encryption built into hard DDR memory controllers helps secure data at rest, while 400G High-Speed Crypto Engines help the device secure user data at up to 2X faster line rates, enabling faster secure data transactions.
AMD Versal Premium Series Gen 2 development tools are expected to be available in Q2 2025, followed by the availability of silicon samples by early 2026. Production shipments are expected to begin in the second half of 2026.
